Programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs), are user-programmable integrated circuits that can be programmed to implement user-defined logic circuits. In a typical FPGA architecture, an array of configurable logic blocks (CLBs) and a programmable interconnect structure are surrounded by a ring of programmable input/output blocks (IOBs). Each of the CLBs, the programmable interconnect structure, and the IOBs includes configuration memory cells, the contents of which determine how the CLB, the programmable interconnect structure, or the IOB is configured. To realize a user-defined circuit, configuration data is loaded into the configuration memory cells such that the CLBs and IOBs are configured to realize particular circuit components used in the user-defined circuit. Configuration data is also loaded into the configuration memory cells of the programmable interconnect structure such that the programmable interconnect structure connects the various configured CLBs and IOBs in a desired manner to realize the user-defined circuit.
FIG. 1 (Prior Art) is a simplified conceptual diagram of one type of modern FPGA 1 available from Xilinx, Inc. of San Jose, Calif. FPGA 1 includes a central matrix of CLB tiles 2 with strips BRAM/Mult (Block Random Access Memory/Multiplier) tiles 3, a microprocessor core 4, DCM (Digital Clock Manager) tiles 5, MGT (multi-gigabit transceiver) tiles 6, and a ring of IOB tiles 7. All of the tiles including the CLB tiles, BRAM/Mult tiles and IOB tiles contain logic circuitry as well as a portion of the programmable interconnect structure of the composite FPGA. This portion of the programmable interconnect structure includes a switch box and a plurality of routing conductor segments. The routing conductor segments of the tiles are fashioned such that when the tiles are placed adjacent to one another, the routing conductor segments of adjacent tiles together form routing conductors of the programmable interconnect structure of the FPGA. These routing conductors allow the logic circuitry within the tiles to be interconnected in the desired way to realize the user-defined circuit.
For additional information on a tile FPGA architecture, see: 1) U.S. Pat. No. 5,914,616 by Young et al.; 2) the Advance Product Specification entitled “Virtex-II Pro Platform FPGAs: Functional Description”, Sep. 27, 2002; 3) Published U.S. Patent Application US2001/0030555-A1 by Wittig et al.; and 4) U.S. Pat. No. 6,396,302, by New et al. The subject matter of these four documents is incorporated herein by reference.
Advanced state-of-the-art FPGA's, such as FPGA 1, are complex and large integrated circuits. As FPGAs have grown in size and become more complex, structures that are not always used in all user-defined designs have been incorporated onto FPGAs. Examples of these structures include large blocks of RAM, microprocessors, and high voltage I/O circuitry. FPGA users often differ in their desire to use these structures.
In the example of FPGA 1 some user-defined designs may, for example, involve additional RAM for use of the microprocessor 4 whereas other user-defined designs would not use such additional RAM. For an FPGA user who does not want or need this extra RAM structure, having to purchase an FPGA that involves this unwanted RAM structure involves an undesirable cost. Accordingly, it is desirable to be able to offer FPGAs both with and without such extra structures that are not universally desired.
In addition to being able to offer FPGAs both with and without such extra structures, it is also desirable to be able to reduce the manufacturing cost of the most advanced state-of-the-art FPGAs. The most advanced FPGAs typically have the most functionality. To provide that functionality, a large integrated circuit is generally required. The size of the integrated circuit can push the limits of current integrated circuit manufacturing technology. The result is that new large FPGAs, when they are first offered, generally have a low manufacturing yield. This low yield translates into a higher manufacturing cost. It would be desirable to be able to produce simpler and therefore more manufacturable FPGAs that nevertheless provide the same functionality as the most advanced state-of-the-art FPGAs.
In addition to FPGAs becoming larger, the logic structures required on FPGAs have become more complex. Some of the functions to be performed by contemporaneous FPGAs are best performed using certain types of circuit structures and processes whereas other functions to be performed by contemporaneous FPGAs are best performed using other types of circuit structures and processes. Complex and expensive integrated circuit manufacturing processes are therefore often necessary to realize all the different types of circuit structures desired on the same FPGA integrated circuit. It would be desirable to reduce the complexity and cost associated with making such FPGAs. A solution is desired.